Method and apparatus for generating parity values
US6981206B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Dec 27, 2005 |
| Priority date | — |
| Expiry date | May 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.