Method and apparatus for building up large scale on chip de-coupling capacitor on standard CMOS/SOI technology
US6982197B2 · kind B2 · utility
4Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2002 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Oct 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The apparatus and method for forming de-coupling capacitors on top of SOC VLSI chip. The introduced large amount of de-coupling capacitor is intended to solve the power delivery problem of highly integrated and powered VLSI chip, especially in the Silicon-On-Insulator (SOI) technology. This invention proposes a design scheme which could utilize virtually unused area to build efficient de-coupling capacitors without introducing additional manufacture cost. This design scheme is especially effective when the VLSI technology is scaled down further.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.