Digital delay-locked loop circuits with hierarchical delay adjustment
US6982578B2 · kind B2 · utility
15Cited by
23References
37Claims
0Family size
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Inventor
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.