Digital frequency-multiplying DLLs
US6982579B2 · kind B2 · utility
30Cited by
23References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Jan 3, 2006 |
| Priority date | — |
| Expiry date | Dec 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.