Circuits and techniques for conditioning differential signals
US6985021B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2003 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Aug 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.