Method of in-wafer testing of monolithic photonic integrated circuits (PICs) formed in a semiconductor wafer
US6985648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F55/18
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of in-wafer testing is provided for a monolithic photonic integrated circuit (PIC) formed in a semiconductor wafer where each such in-wafer circuit comprises two or more integrated electro-optic components, one of each in tandem forming a signal channel in the circuit. The method includes the provision of a first integrated photodetector at a rear end of each signal channel and a second integrated photodetector at forward end of each signal channel. Then, the testing is accomplished, first, by sequentially operating a first of a selected channel electro-optic component in a selected circuit to monitor light output from a channel via its first corresponding channel photodetector and adjusting its operating characteristics by detecting that channel electro-optic component output via its second corresponding channel photodetector to provide first calibration data. Second, by sequentially operating a second of a selected channel electro-optic component in the selected circuit to monitor signal output from the second selected channel electro-optic component via its second corresponding channel photodetector and adjusting its operating characteristics by detecting that channel e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.