System-on-a-Chip structure having a multiple channel bus bridge
US6985988B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | Jan 10, 2006 |
| Priority date | — |
| Expiry date | Jan 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-a-chip integrated circuit structure includes a bridge having a plurality of channels, a processor local bus connected to the bridge (wherein the bridge includes a first channel dedicated to the processor local bus), at least one logic device connected to the processor local bus, a peripheral device bus connected to the bridge (wherein the bridge includes a second channel dedicated to the peripheral device bus), at least one peripheral device connected to the peripheral device bus, at least one memory unit connected to the bridge (wherein the bridge includes a third channel dedicated to the memory unit), and at least one input/output unit connected to the bridge (wherein the bridge includes a fourth channel dedicated to the input/output unit).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.