Pascal A. Nsame
30Patents
5h-index
34Co-inventors
69Inventor score
Filing activity: Nov 9, 2000 → Jan 3, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6985988B1 | System-on-a-Chip structure having a multiple channel bus bridge | Physics | 18 | Expired |
| US8201038B2 | Integrating design for reliability technology into integrated circuits | Physics | 14 | Active |
| US7849362B2 | Method and system of coherent design verification of inter-cluster interactions | Physics | 10 | Active |
| US6662352B2 | Method of assigning chip I/O's to package channels | Physics | 6 | Expired |
| US8279861B2 | Real-time VoIP communications using n-Way selective language processing | Electricity | 5 | Active |
| US9310426B2 | On-going reliability monitoring of integrated circuit chips in the field | Physics | 5 | Active |
| US9064087B2 | Semiconductor device reliability model and methodologies for use thereof | Physics | 5 | Active |
| US8943444B2 | Semiconductor device reliability model and methodologies for use thereof | Physics | 4 | Active |
| US7765351B2 | High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips | Physics | 3 | Active |
| US8086832B2 | Structure for dynamically adjusting pipelined data paths for improved power management | Emerging Cross-Sectional Technologies | 3 | Active |
| US9739824B2 | Optimization of integrated circuit reliability | Physics | 2 | Active |
| US7711534B2 | Method and system of design verification | Physics | 2 | Active |
| US9557378B2 | Method and structure for multi-core chip product test and selective voltage binning disposition | Physics | 2 | Active |
| US9058250B2 | In-situ computing system failure avoidance | Physics | 1 | Active |
| US9880892B2 | System and method for managing semiconductor manufacturing defects | Physics | 1 | Active |
| US10989754B2 | Optimization of integrated circuit reliability | Physics | 1 | Active |
| US10564214B2 | Optimization of integrated circuit reliability | Physics | 1 | Active |
| US8499140B2 | Dynamically adjusting pipelined data paths for improved power management | Emerging Cross-Sectional Technologies | 1 | Active |
| US9367493B2 | Method and system of communicating between peer processors in SoC environment | Physics | 1 | Active |
| US9043889B2 | Method and apparatus for secure and reliable computing | Physics | 0 | Active |
| US10089161B2 | System and method for managing semiconductor manufacturing defects | Physics | 0 | Active |
| US7495492B2 | Dynamic latch state saving device and protocol | Physics | 0 | Active |
| US8729920B2 | Circuit and method for RAS-enabled and self-regulated frequency and delay sensor | Physics | 0 | Active |
| US11054459B2 | Optimization of integrated circuit reliability | Physics | 0 | Active |
| US8819460B2 | Dynamic energy management | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.