Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors
US6987043B2 · kind B2 · utility
10Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Feb 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.