Driver for an external FET with high accuracy and gate voltage protection
US6987403B2 · kind B2 · utility
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15References
10Claims
0Family size
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Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Jun 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45701
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for driving an external FET has a differential amplification stage supplied by a first and second operating potential. An output load resistor is included in a current flow path in which the current is controlled by the voltage between two input terminals of the amplification stage. The current is substantially independent of variations of the first or second operating potentials. The output load resistor is connected between the gate and the source of the external FET 12.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.