Analog delay locked loop with tracking analog-digital converter
US6987409B2 · kind B2 · utility
19Cited by
13References
18Claims
0Family size
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Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.