Error-correction memory architecture for testing production errors
US6988237B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2004 |
| Grant date | Jan 17, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.