Trench formation in semiconductor integrated circuits (ICs)
US6989317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Oct 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel trench etching method for etching trenches of different depths which are self-aligned to one another is presented. The method comprises the steps of (a) creating first and second trenches of a same depth in a dielectric layer, wherein the second trench is wider than the first trench, (b) forming a conformal gapfill layer on top of the dielectric layer such that the conformal gapfill layer is thicker in the first trench than in the second trench, (c) etching back the conformal gapfill layer until a bottom wall of the second trench is exposed to the atmosphere while a bottom wall of the first trench is still covered by the conformal gapfill layer, (d) etching further into the dielectric layer via the second trench. As a result, the second trench is deeper than the first trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.