Inventor · Wappingers Falls, NY, US

Jay William Strane

40Patents
7h-index
71Co-inventors
72Inventor score

Filing activity: Jun 6, 2002 → Jan 6, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7041571B2 Air gap interconnect structure and method of manufacture Electricity 52 Expired
US8421077B2 Replacement gate MOSFET with self-aligned diffusion contact Electricity 32 Active
US8188574B2 Pedestal guard ring having continuous M1 metal barrier connected to crack stop Electricity 17 Active
US8101518B2 Method and process for forming a self-aligned silicide contact Electricity 10 Active
US6887785B1 Etching openings of different depths using a single mask layer method and structure Electricity 9 Expired
US7544610B2 Method and process for forming a self-aligned silicide contact Electricity 9 Expired
US6809027B2 Self-aligned borderless contacts Electricity 8 Expired
US8299455B2 Semiconductor structures having improved contact resistance Electricity 7 Active
US6989317B1 Trench formation in semiconductor integrated circuits (ICs) Electricity 7 Expired
US6806177B2 Method of making self-aligned borderless contacts Electricity 6 Expired
US8685809B2 Semiconductor structures having improved contact resistance Electricity 5 Active
US8039382B2 Method for forming self-aligned metal silicide contacts Chemistry; Metallurgy 5 Active
US7618891B2 Method for forming self-aligned metal silicide contacts Chemistry; Metallurgy 4 Active
US9666474B2 Uniform dielectric recess depth during fin reveal Electricity 3 Active
US7790553B2 Methods for forming high performance gates and structures thereof Electricity 3 Active
US7601646B2 Top-oxide-early process and array top oxide planarization Electricity 2 Active
US10535550B2 Protection of low temperature isolation fill Electricity 1 Active
US9984935B2 Uniform dielectric recess depth during fin reveal Electricity 1 Active
US10636709B2 Semiconductor fins with dielectric isolation at fin bottom Electricity 1 Active
US11043429B2 Semiconductor fins with dielectric isolation at fin bottom Electricity 0 Active
US12310090B2 CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor Electricity 0 Active
US9984916B2 Uniform dielectric recess depth during fin reveal Electricity 0 Active
US11217692B2 Vertical field effect transistor with bottom spacer Electricity 0 Active
US11251287B2 Self-aligned uniform bottom spacers for VTFETS Electricity 0 Active
US12183740B2 Stacked field-effect transistors Performing Operations; Transporting 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.