Memory device having an electron trapping layer in a high-K dielectric gate stack
US6989565B1 · kind B1 · utility
49Cited by
4References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.