Strained-channel isolated-gate field effect transistor, process for making same and resulting integrated circuit

US6989570B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Thomas Skotnicki · Meylan, FR
• Daniel Bensahel · Grenoble, FR

Key dates

• Filing date: Mar 31, 2003
• Grant date: Jan 24, 2006
• Expiry date: Apr 16, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6748

Abstract

A transistor is located on a base layer 1 resting on a semiconductor substrate SB and formed from a relaxed silicon-germanium layer, and includes, under the isolated gate 7, a first strained silicon layer 2 resting on the base layer 1, surmounted by a buried insulating layer 10, surmounted by a second strained silicon layer 4 extending between the source S and drain D regions.