Method for making a multi-die chip
US6989582B2 · kind B2 · utility
2Cited by
27References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jun 6, 2023 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B2201/045
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention generally relates to a die perimeter region of a die having a microelectromechanical assembly fabricated thereon. This die perimeter region may be configured to facilitate electrically interconnecting adjacent die on a wafer. Moreover, this die perimeter region may be configured to facilitate separating the die from a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.