Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers
US6989607B2 · kind B2 · utility
0Cited by
9References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.