System and method for synchronizing divide-by counters

US6989696B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Rolf Hilgendorf · Eppelheim, DE
• Jens Kuenzer · Eppelheim, DE
• Cedric Lichtenau · Stuttgart, DE
• Thomas Pflueger · Echterdingen, DE
• Mathew I. Ringler · Burlington, US
• Gerard M. Salem · Willsboro, US
• Peter A. Sandon · South Burlington, US
• Dana J. Thygesen · Vergennes, US
• Ulrich Weiss · Holzgerlingen, DE

Key dates

• Filing date: Nov 19, 2003
• Grant date: Jan 24, 2006
• Expiry date: Dec 8, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/06
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.