Ultra low power adder with sum synchronization
US6990509B2 · kind B2 · utility
2Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Jan 24, 2006 |
| Priority date | — |
| Expiry date | Nov 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs until the corresponding carry signals have reached their final values, which is achieved by adding a synchronization circuitry to the sum calculation path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.