Integrated semiconductor memory with a selection transistor formed at a ridge

US6992345B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gerhard Enders · Glen Allen, US
• Andreas Spitzer · Ottobrunn, DE

Key dates

• Filing date: Dec 5, 2003
• Grant date: Jan 31, 2006
• Expiry date: Dec 5, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

An integrated semiconductor memory is disclosed having selection transistors which can be formed at a respective ridge. The ridge can be arranged on an insulation layer. In the ridge the first source/drain region can be formed at one lateral end of the ridge and the second source/drain region can be formed at another lateral end of the ridge. The longitudinal sides of the ridge and a top side of the ridge can be covered with a layer stack including a gate dielectric and a gate electrode. High write-read currents can be achieved in the on state of the selection transistors and leakage currents occurring in the off state can be reduced.