Apparatus and method for handling of multi-level circuit design data
US6993733B2 · kind B2 · utility
9Cited by
32References
119Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Jan 31, 2006 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be found much later in the design or manufacturing cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.