Patent assignee · US · COMPANY

Atrenta, Inc.

47Patents
39Active
47Granted
48Portfolio score

Filing activity: Apr 9, 2002 → Dec 13, 2013 · 11 expiring within 5 years

Most-cited patents

PatentTitleAreaCited byStatus
US7076748B2 Identification and implementation of clock gating in the design of integrated circuits Physics 41 Expired
US8448111B2 System and method for metastability verification of circuits of an integrated circuit Physics 28 Active
US7073146B2 Method for clock synchronization validation in integrated circuit design Physics 27 Expired
US8839171B1 Method of global design closure at top level and driving of downstream implementation flow Physics 16 Active
US7152216B2 Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains Physics 12 Expired
US8930863B2 System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist Emerging Cross-Sectional Technologies 11 Active
US6993733B2 Apparatus and method for handling of multi-level circuit design data Physics 9 Expired
US7216321B2 Pattern recognition in an integrated circuit design Physics 9 Expired
US6876934B2 Method for determining fault coverage from RTL description Physics 8 Expired
US7650581B2 Method for modeling and verifying timing exceptions Physics 8 Active
US9135382B1 Systems, methods, and media for assertion-based verification of devices Physics 8 Active
US7277840B2 Method for detecting bus contention from RTL description Physics 8 Expired
US8533647B1 Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design Physics 7 Active
US7536662B2 Method for recognizing and verifying FIFO structures in integrated circuit designs Physics 6 Active
US8856706B2 System and method for metastability verification of circuits of an integrated circuit Physics 6 Active
US7349835B2 Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits Physics 5 Expired
US7506292B2 Method for clock synchronization validation in integrated circuit design Physics 5 Active
US7546559B2 Method of optimization of clock gating in integrated circuit designs Physics 5 Active
US7941679B2 Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design Physics 5 Active
US8285527B2 Method and system for equivalence checking Physics 5 Active
US8863058B2 Characterization based buffering and sizing for system performance optimization Physics 5 Active
US7451427B2 Bus representation for efficient physical synthesis of integrated circuit designs Physics 4 Active
US8042085B2 Method for compaction of timing exception paths Physics 4 Active
US8656326B1 Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design Physics 4 Active
US8782582B1 Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis Emerging Cross-Sectional Technologies 3 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.