Method and structure for double dose gate in a JFET
US6995052B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.