Semiconductor memory device including multi-layer gate structure
US6995414B2 · kind B2 · utility
12Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Feb 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.