Integrated semiconductor storage with at least a storage cell and procedure
US6995418B2 · kind B2 · utility
3Cited by
5References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 2004 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | May 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
The invention relates to an integrated semiconductor memory with at least one memory cell having at least one transistor which forms an inversion channel in the switched-on state. The transistor comprises a structure element having a first source/drain region, a second source/drain region and a region arranged between the first and the second source/drain region, the structure element is insulated from a semiconductor substrate by an insulation layer, a gate dielectric being arranged on the structure element and a word line being arranged on the gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.