Devices for synchronizing clock signals
US6996026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2004 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock signal synchronizing device includes a first delay unit with variable delay time connected to an input circuit with a first delay time which receives a first clock signal and outputs a second clock signal. A second delay unit has a fixed delay time portion corresponding to the first delay time, and an additional variable delay time portion. A first phase comparison unit has a first input connected to the output of the input circuit, and a second input connected to the output of the second delay unit. The output signal controls the delay time of the first delay unit. A copy of the input circuit has an input connected to the output of the first delay unit. A second phase comparison unit has an input connected to the output of the copy, and an output signal controls the variable delay time portion of the second delay unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.