Practical methodology for early buffer and wire resource allocation
US6996512B2 · kind B2 · utility
46Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2001 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Oct 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.