Retrieval of all tag entries of cache locations for memory address and determining ECC based on same
US6996675B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Nov 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The retrieval of all tag entries of cache locations for a memory address is disclosed, as well as the determining of an error correcting code (ECC) for the tag entries based thereon. Tag entries of tag memory that correspond to possible cache locations within an n-way associative cache are retrieved for a memory address. An ECC for the tag entries, based on the entries, is determined, and is stored as part of the entries within the tag memory. The n-way associative cache may be a two-way associative cache, such that there are two tag entries corresponding to two possible cache locations within the cache for the memory address. The ECC for the two tag entries are thus based on the two tag entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.