Bruce M. Gilbert
20Patents
10h-index
15Co-inventors
68Inventor score
Filing activity: Jun 27, 1996 → Jan 27, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7124410B2 | Distributed allocation of system hardware resources for multiprocessor systems | Physics | 84 | Expired |
| US5900020A | Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency | Physics | 49 | Expired |
| US6295584A | Multiprocessor computer system with memory map translation | Physics | 42 | Expired |
| US6598120B1 | Assignment of building block collector agent to receive acknowledgments from other building block agents | Physics | 34 | Expired |
| US7051180B2 | Masterless building block binding to partitions using identifiers and indicators | Physics | 25 | Expired |
| US6591370B1 | Multinode computer system with distributed clock synchronization system | Electricity | 24 | Expired |
| US6041376A | Distributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested data | Physics | 20 | Expired |
| US8578130B2 | Partitioning of node into more than one partition | Physics | 17 | Expired |
| US6636944B1 | Associative cache and method for replacing data entries having an IO state | Physics | 16 | Expired |
| US6910108B2 | Hardware support for partitioning a multiprocessor system to allow distinct operating systems | Physics | 13 | Expired |
| US6973544B2 | Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system | Physics | 6 | Expired |
| US7383464B2 | Non-inline transaction error correction | Physics | 3 | Expired |
| US7000089B2 | Address assignment to transaction for serialization | Emerging Cross-Sectional Technologies | 2 | Expired |
| US6996675B2 | Retrieval of all tag entries of cache locations for memory address and determining ECC based on same | Physics | 2 | Expired |
| US7827449B2 | Non-inline transaction error correction | Physics | 2 | Active |
| US7210018B2 | Multiple-stage pipeline for transaction conversion | Physics | 2 | Expired |
| US6996665B2 | Hazard queue for transaction pipeline | Physics | 2 | Expired |
| US6823498B2 | Masterless building block binding to partitions | Physics | 2 | Expired |
| US8250330B2 | Memory controller having tables mapping memory addresses to memory modules | Physics | 2 | Active |
| US6934835B2 | Building block removal from partitions | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.