Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6996766B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Feb 7, 2006 |
| Priority date | — |
| Expiry date | Jan 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is configured to decode the encoded data block and to detect a failure of one of the plurality of memory devices responsive to decoding the encoded data block. The data remap control circuit is configured to cause a remap of each of a plurality of encoded data blocks to avoid storing bits in the failing memory device. A memory controller may also be configured to detect and correct a first failed memory device and a second failed memory device of the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.