Mechanically robust interconnect for low-k dielectric material using post treatment
US6998216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/143
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.