Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS
US6998304B2 · kind B2 · utility
3Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Mar 1, 2004 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method for integrated processing of a high Voltage MOSFET device and a split gate MOSFET device whereby a novel method is provided to form the split gate device and the high voltage MOSFET device in parallel processing steps including an oxide formation step whereby an oxide spacer layer in a split gate device is formed using about the same overall thermal budget while forming in parallel a thick gate oxide for a an embedded high voltage MOSFET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.