Processes for making a single election transistor with a vertical channel
US6998310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2002 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/962
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
This invention relates to a process for a manufacturing a Coulomb blockade transistor. The process comprises the following steps in sequence: deposition on an insulating substrate of a source layer, a tunnel-insulating layer and an alternating stack of at least one conducting layer and at least one insulating layer, a first etching of the stack to form a filiform tab, coating of the filiform tab with an electrically insulating coating material, a second etching of the tab of the stack to form a pillar, the second etching preserving the coating material to define a groove on each side of the pillar, the formation of at least one isolated grid in the groove, and the formation of a drain in contact with one end of the pillar opposite the source layer, through at least one tunnel-insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.