Nitrided STI liner oxide for reduced corner device impact on vertical device performance
US6998666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2004 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jan 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.