Delay-lock-loop with improved accuracy and range
US6999547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2002 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Delay-Lock-Loop circuit and a method for producing a phase shift comprises a phase generator producing a first and second clock signal having a first and second rising edge, respectively, wherein a timing difference between the first and second rising edges is equal to a desired cycle time; a delay circuit operable to receive the first clock signal and to produce a delayed clock signal; and a latch element connected to the delay circuit, and operable to check whether the delayed clock signal is delayed by an amount equal to the desired cycle time; a plurality of serially connected binary-weighted inverters connected to the latch element, which are operable to adjust the delay of the delayed clock signal to be equal to the desired cycle time; and a phase-shifted delay circuit connected to the delay circuit, and operable to produce multiple degrees of phase shift of the delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.