Redundancy register architecture for soft-error tolerance and methods of making the same
US7000155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2003 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Oct 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.