Method, apparatus, and program for block-based static timing analysis with uncertainty
US7000205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Feb 14, 2006 |
| Priority date | — |
| Expiry date | Jul 7, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.”
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.