Method and apparatus for filling interlayer vias on ferroelectric polymer substrates
US7001782B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.