Method of manufacturing a shallow trench isolation structure with low trench parasitic capacitance
US7001823B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2001 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.