Ultra-thin body super-steep retrograde well (SSRW) FET devices
US7002214B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2004 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.