Microelectronic component with reduced parasitic inductance and method of fabricating
US7002249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/916
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package is disclosed which includes inter-digitated input and output bond wires configured to increase the negative mutual inductive coupling between the wires, thus reducing the overall parasitic inductance of the device. In one embodiment, the microelectronic component includes a semiconductor device coupled to a substrate, such as a lead frame, a first set of bond wires connected to the semiconductor device for providing current flow into the semiconductor device, and a second set of bond wires that are in a current loop with the first set of bond wires and are connected to the semiconductor device for providing current flow out of the semiconductor device, wherein the first and second set of bond wires are configured in an inter-digitated pattern to increase the magnitude of mutual inductive coupling between the first and second set of bond wires. In one embodiment, the semiconductor device comprises a single semiconductor chip and the lead frame comprises a Quad Flat No-Lead (QFN) lead frame. Other embodiments include multiple chips and/or multiple lead frames.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.