Nonvolatile semiconductor memory device
US7002848B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Feb 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of “write processing” and “upper limit determination processing” to each threshold voltage distribution, after the end of write processing for “10” and “00” distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the “10” and “00” distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are n…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.