Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process
US7003738B2 · kind B2 · utility
22Cited by
7References
38Claims
0Family size
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Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Jul 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.