Method of achieving timing closure in digital integrated circuits by optimizing individual macros
US7003747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Feb 21, 2006 |
| Priority date | — |
| Expiry date | Oct 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.