Patrick M. Williams
17Patents
8h-index
40Co-inventors
72Inventor score
Filing activity: Apr 24, 1998 → Sep 10, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7093208B2 | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices | Physics | 220 | Expired |
| US7010763B2 | Method of optimizing and analyzing selected portions of a digital integrated circuit | Physics | 23 | Expired |
| US6629298B1 | Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design | Physics | 16 | Expired |
| US6022231A | Pre-bussed rigid conduit electrical distribution system | Electricity | 13 | Expired |
| US7627836B2 | OPC trimming for performance | Physics | 11 | Expired |
| US7971171B2 | Method and system for electromigration analysis on signal wiring | Physics | 11 | Active |
| US7325210B2 | Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect | Physics | 10 | Expired |
| US7003747B2 | Method of achieving timing closure in digital integrated circuits by optimizing individual macros | Physics | 8 | Expired |
| US10360338B2 | Method for improving capacitance extraction performance by approximating the effect of distant shapes | Physics | 4 | Active |
| US7743355B2 | Method of achieving timing closure in digital integrated circuits by optimizing individual macros | Physics | 3 | Active |
| US8239804B2 | Method for calculating capacitance gradients in VLSI layouts using a shape processing engine | Physics | 3 | Active |
| US6176719A | Bolted electrical connecting device for multiple electrical conductors | Electricity | 1 | Expired |
| US10248753B2 | Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values | Physics | 1 | Active |
| US10254784B1 | Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities | Electricity | 1 | Active |
| US10565336B2 | Pessimism reduction in cross-talk noise determination used in integrated circuit design | Physics | 1 | Active |
| US10552570B2 | Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor values | Physics | 0 | Active |
| US10169514B2 | Approximation of resistor-capacitor circuit extraction for thread-safe design changes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.