Method for a parallel production of an MOS transistor and a bipolar transistor

US7005337B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Adrian Berthold · Birkenfeld, DE
• Josef Boeck · Putzbrunn, DE
• Wolfgang Klein · Zorneding, DE
• Juergen Holz · Munich, DE

Key dates

• Filing date: Feb 6, 2004
• Grant date: Feb 28, 2006
• Expiry date: Feb 6, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method includes generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure includes an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which includes a conductive layer and a mask layer on the conductive layer. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed. Further, the method includes simultaneous generation of isolating spacing layers on side walls of the gate electrode layer in the MOS area and the conductive layer in the bipolar area by depositing a first and second spacing layer. In the MOS area, the isolating spacing layers serve for defining areas to be doped and in the bipolar area for the isolation of a base area and an emitter area. Subsequently, selective etching of the first spacing layer and the second spacing layer is …