Double-gate flash memory device
US7005700B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jan 6, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jan 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The conventional flash memory device is fabricated by the MOS processing technology on a bulk substrate and has a similar configuration to an MOS device.While the conventional CMOS device has a superior scaling down characteristic, the scaling down characteristic of a flash memory device is poor due to the inability to reduce the thickness below 7 nm or 8 nm for the tunneling oxide film where the charges in the channel are tunneled into the floating electrode through the tunneling oxide.In order to resolve this problem, the present invention, instead of a SOI wafer, uses a cheaper bulk silicon wafer with lower defect density. A wall shape Fin active region where the channel and the source/drain are formed is connected to the bulk silicon substrate by which floating body effect and heat conduction problem are resolved. a flash memory device is fabricated by forming a tunneling oxide film on side surfaces of the Fin active and a floating (storage) electrode where the charges could be stored.The above structure has a superior scaling down characteristic and enhanced memory performance due to a double-gate flash memory device structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.