Conductor line stack having a top portion of a second layer that is smaller than the bottom portion
US7005744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over the layer of first material, the layer of second material having an upper portion and a lower portion. A pair of first spacers is disposed on sidewalls of the upper portion, wherein the lower portion has width defined by a combined width of the upper portion and the pair of first spacers. A pair of second spacers is formed on sidewalls of the first spacers, the lower portion and the layer of first material. The conductor line stack structure is well adapted for formation of a borderless bitline contact in contact therewith.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.