Xiangdong Chen
166Patents
16h-index
157Co-inventors
89Inventor score
Filing activity: Feb 4, 1997 → Jul 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7057216B2 | High mobility heterojunction complementary field effect transistors and methods thereof | Electricity | 127 | Expired |
| US8129797B2 | Work function engineering for eDRAM MOSFETs | Electricity | 119 | Active |
| US6972461B1 | Channel MOSFET with strained silicon channel on strained SiGe | Emerging Cross-Sectional Technologies | 79 | Expired |
| US7104250B1 | Injection spray pattern for direct injection spark ignition engines | Emerging Cross-Sectional Technologies | 50 | Expired |
| US7368358B2 | Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body | Electricity | 47 | Active |
| US7045873B2 | Dynamic threshold voltage MOSFET on SOI | Electricity | 44 | Expired |
| US8928128B2 | Semiconductor package with integrated electromagnetic shielding | Electricity | 35 | Active |
| US6744083B2 | Submicron MOSFET having asymmetric channel profile | Electricity | 31 | Expired |
| US8299545B2 | Method and structure to improve body effect and junction capacitance | Electricity | 29 | Active |
| US7002209B2 | MOSFET structure with high mechanical stress in the channel | Electricity | 26 | Expired |
| US9059179B2 | Semiconductor package with a bridge interposer | Electricity | 22 | Active |
| US9831272B2 | Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches | Electricity | 22 | Active |
| US7867839B2 | Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors | Electricity | 19 | Active |
| US8923070B2 | FinFET based one-time programmable device | Electricity | 19 | Active |
| US9431371B2 | Semiconductor package with a bridge interposer | Electricity | 17 | Active |
| US7294879B2 | Vertical MOSFET with dual work function materials | Electricity | 16 | Expired |
| US7361539B2 | Dual stress liner | Electricity | 14 | Active |
| US8466473B2 | Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs | Electricity | 14 | Active |
| US9379058B2 | Grounding dummy gate in scaled layout design | Electricity | 12 | Active |
| US7635620B2 | Semiconductor device structure having enhanced performance FET device | Electricity | 11 | Active |
| US7102914B2 | Gate controlled floating well vertical MOSFET | Electricity | 11 | Expired |
| US7432553B2 | Structure and method to optimize strain in CMOSFETs | Electricity | 11 | Expired |
| US8062951B2 | Method to increase effective MOSFET width | Electricity | 10 | Active |
| US8441000B2 | Heterojunction tunneling field effect transistors, and methods for fabricating the same | Electricity | 9 | Expired |
| US9331016B2 | SOC design with critical technology pitch alignment | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.